1. Technical Field
The present invention relates to a substrate, and more particularly, to a chip embedded substrate and a method of manufacturing the same.
2. Description of the Related Art
In accordance with a recent trend of miniaturization, thinness, and lightness of an electronic device, miniaturization and lightness of a printed circuit board (PCB) is also required. In a printed circuit board for package, an embedding substrate in which a passive element such as a capacitor as well as an active element such as an integrated chip (IC) are embedded in the printed circuit board has been gradually increased.
In the case in which a chip is embedded in the substrate, there are advantages that a size of an electronic component is reduced to help miniaturization and lightness of a product, an operation frequency of a circuit may be increased by removing parasitic components, and the effect of external electromagnetic wave causing noise may be intercepted.
Further, as a market of portable electronic devices such as smartphones, smart pads, and the like is explosively growing, a chip embedded substrate capable of meeting a specification requirement of slimness and lightness products has been highlighted.
As the related art in which cavities are processed in the substrate and the chips are then embedded in the cavities, there is a technology (hereinafter, referred to as ‘the related art’) disclosed in Korean Patent Laid-Open Publication No. 10-2004-0073606. The related art has a gist of a technology of manufacturing the cavity penetrating through the substrate and then attaching an adhesive tape to a lower surface of the substrate, seating the aligned chips in the cavity and then filling the cavity with a resin, and removing the adhesive tape once the chips are fixed.
According to the manufacturing method described above, wiring layers are provided to upper and lower portions of a core layer in which the components are embedded and a build-up process is performed for the upper and lower portions of the core layer, thereby completing a multilayer substrate. In this case, there is a limit in implementing high density of the wiring layer.